Structure and formation method of semiconductor device structure with gate stack

ABSTRACT

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-1D are perspective views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

FIGS. 2A-2D are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

FIG. 3 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

FIG. 4 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

FIGS. 5A-5B are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.

FIG. 6 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

FIG. 7 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Some embodiments of the disclosure are described. FIGS. 1A-1D are perspective views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. FIGS. 2A-2D are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. In some embodiments, some of the cross-sectional views in FIGS. 2A-2D correspond to the cross-sectional views taken along the line I-I in FIGS. 1B-1D. Additional operations can be provided before, during, and/or after the stages described in FIGS. 1A-1D or FIGS. 2A-2D. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments.

As shown in FIGS. 1A and 2A, one or more fin structures including a fin structure 120 are formed over a semiconductor substrate 100, in accordance with some embodiments. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the semiconductor substrate 100 is a silicon wafer. The semiconductor substrate 100 may include silicon or another elementary semiconductor material such as germanium. In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable material, or a combination thereof.

In some embodiments, the semiconductor substrate 100 includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof.

In some embodiments, multiple recesses (or trenches) are formed in the semiconductor substrate 100. As a result, multiple fin structures including the fin structure 120 are formed between the recesses. For simplicity, only one of the fin structures (the fin structure 120) is shown in FIGS. 1A and 2A. In some embodiments, one or more photolithography and etching processes are used to form the recesses.

As shown in FIGS. 1A and 2A, isolation features 130 are formed in the recesses to surround a lower portion of the fin structure 120, in accordance with some embodiments. In some embodiments, the isolation features 130 continuously surround the lower portion of the fin structures 102. In some embodiments, the isolation features 130 surround lower portions of other fin structures formed on the semiconductor substrate 100. The isolation features 130 are used to define and electrically isolate various device elements formed in and/or over the semiconductor substrate 100. In some embodiments, the isolation features 130 include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

In some embodiments, each of the isolation features 130 has a multi-layer structure. In some embodiments, the isolation features 130 are made of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-K dielectric material, another suitable material, or a combination thereof. In some embodiments, an STI liner (not shown) is formed to reduce crystalline defects at the interface between the semiconductor substrate 100 and the isolation features 130. The STI liner matin also be used to reduce crystalline defects at the interface between the fin structures and the isolation features 130.

In some embodiments, a dielectric material layer is deposited over the semiconductor substrate 100. The dielectric material layer covers the fin structures including the fin structure 120 and fills the recesses between the fin structures. In some embodiments, a planarization process is performed to thin down the dielectric material layer. For example, the dielectric material layer is thinned until the fin structure 120 is exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, another applicable process, or a combination thereof. Afterwards, the dielectric material layer is etched back to be below the top of the fin structure 120. As a result, the isolation features 130 are formed. The fin structures including the fin structure 120 protrude from top surfaces of the isolation features 130, as shown in FIGS. 1A and 2A in accordance with some embodiments.

As shown in FIGS. 1B and 2A, a dummy gate stack 155 including a gate dielectric layer 140 and a gate electrode 150 are formed over the fin structure 120 and the semiconductor substrate 100, in accordance with some embodiments. The dummy gate stack 155 covers a portion of the fin structure 120. In some embodiments, the dummy gate stack 155 covers portions of multiple fin structures including the fin structure 120.

In some embodiments, the gate dielectric layer 140 is made of silicon oxide, silicon nitride, silicon oxynitride, dielectric material with a high dielectric constant (high-K), another suitable dielectric material, or a combination thereof. Examples of high-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof. In some embodiments, the gate dielectric layer 140 is a dummy gate dielectric layer which will subsequently be removed. In some other embodiments, the gate dielectric layer 140 is not formed.

In some embodiments, the gate dielectric layer 140 is deposited over the isolation features 103 and the fin structure 120 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof.

Afterwards, the gate electrode 150 is formed over the gate dielectric layer 140 to cover a portion of the fin structure 120, as shown in FIGS. 1B and 2A in accordance with some embodiments. In some embodiments, the gate electrode 150 is a dummy gate electrode which will be replaced with a metal gate electrode. In some embodiments, the gate electrode 150 is made of polysilicon.

In some embodiments, a gate electrode layer is deposited over the gate dielectric layer 140. The gate electrode layer may be deposited using a CVD process or another applicable process. In some embodiments, the gate electrode layer is made of polysilicon. Afterwards, a patterned hard mask layer (not shown) is formed over the gate electrode layer, in accordance with some embodiments. The patterned hard mask layer is used to pattern the gate electrode layer into one or more gate electrodes including the gate electrode 150. One or more etching processes may be used to etch the gate electrode layer through openings of the patterned hard mask layer so as to form the dummy gate stack 155.

Afterwards, spacer elements 160 are formed over sidewalls of the gate electrode 150, as shown in FIGS. 1B and 2A in accordance with some embodiments. The spacer elements 160 may be used to assist in a subsequent formation of source/drain features. In some embodiments, the spacer elements 160 include one or more layers. In some embodiments, the spacer elements 160 are made of a dielectric material. The dielectric material may include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

In some embodiments, a spacer material layer is deposited over the dummy gate stack 155 using a CVD process, a PVD process, a spin-on process, another applicable process, or a combination thereof. Afterwards, the spacer material layer is partially removed using an etching process, such as an anisotropic etching process. As a result, remaining portions of the spacer material layer on the sidewalls of the dummy gate stack 155 form the spacer elements 160, as shown in FIGS. 1B and 2A. In some embodiments, the spacer elements 160 are formed after the portion of the gate dielectric layer 140 not covered by the gate electrode 150 is removed. In some embodiments, the gate dielectric layer 140 not covered by the gate electrode 150 is removed together with the spacer material layer during the etching process for forming the spacer elements 160.

Afterwards, source/drain features 170 are formed on the fin structure 120, as shown in FIGS. 1B and 2A in accordance with some embodiments. In some embodiments, the fin structure 120 not covered by the gate electrode 150 and the spacer elements 160 is partially removed to form recesses using, for example, an etching process. The bottoms of the recesses may be below the top surfaces of the isolation features 130. Afterwards, source/drain features 170 are formed in the recesses. In some embodiments, the source/drain features 170 are epitaxially grown features formed using an epitaxial growth process. In some embodiments, the source/drain features 170 protrude from the recesses. In some embodiments, the source/drain features 170 are also used as stressors that can apply strain or stress on the channel region between the source/drain features 170. The carrier mobility may be improved accordingly.

As shown in FIGS. 1B and 2A, a dielectric layer 180 is then formed to surround the dummy gate stack 155 and the source/drain features 170, in accordance with some embodiments. For a better understanding of the disclosure, the dielectric layer 180 in FIG. 1B is illustrated in dashed lines such that the elements covered by the dielectric layer 180 is visible. In some embodiments, a dielectric material layer is deposited to cover the source/drain features 170, the spacer elements 160, and the gate electrode 150.

In some embodiments, the dielectric material layer is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof. In some embodiments, the dielectric material layer is deposited using a CVD process, an ALD process, a spin-on process, a spray coating process, another applicable process, or a combination thereof.

Afterwards, a planarization process may be used to partially remove the dielectric material layer. The dielectric material layer may be partially removed until the gate electrode 150 is exposed. As a result, the dielectric layer 180 is formed. In some embodiments, the planarization process includes a CMP process, a grinding process, a dry polishing process, an etching process, another applicable process, or a combination thereof.

As shown in FIGS. 1C and 2B, the gate electrode 150 and a portion of the gate dielectric layer 140 are removed to form a recess 210, in accordance with some embodiments. The recess 210 is surrounded by the dielectric layer 180 and positioned between the spacer elements 160. The recess 210 exposes the fin structure 120. One or more etching processes may be used to form the recess 210. In some embodiments, a portion of the gate dielectric layer 140 directly under the spacer elements 160 remains without being removed.

As shown in FIG. 2C, an interfacial layer 181 is deposited over the dielectric layer 180 and sidewalls and a bottom of the recess 210, in accordance with some embodiments. In some embodiments, the interfacial layer 181 conformally covers the fin structure 120 exposed by the recess 210 and the sidewalls and bottom of the recess 210. The interface layer 181 may be used to improve adhesion between the fin structure 120 and a subsequently formed gate dielectric layer. In some embodiments, the interfacial layer is made of a semiconductor oxide material, such as silicon oxide, germanium oxide, or silicon germanium oxide. In some embodiments, the interfacial layer 181 is deposited using an ALD process, a CVD process, a thermal oxidation process, another applicable process, or a combination thereof.

As shown in FIG. 2C, a gate dielectric layer 182 is deposited over the interfacial layer 181, in accordance with some embodiments. In some embodiments, the gate dielectric layer 182 conformally covers the fin structure 120 and the sidewalls and bottom of the recess 210. In some embodiments, the gate dielectric layer 182 and the gate dielectric layer 140 under the spacer elements 180 are made of different materials. In some embodiments, the gate dielectric layer 182 is made of a high-K dielectric material. The high-K dielectric material may include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof. In some embodiments, the gate dielectric layer 182 is deposited using an ALD process, a CVD process, another applicable process, or a combination thereof.

Afterwards, a halogen source layer 184 is formed over the gate dielectric layer 182, as shown in FIG. 2C in accordance with some embodiments. In some embodiments, the halogen source layer 184 is in direct contact with the gate dielectric layer 182. In some other embodiments, a material layer (not shown) is formed between the halogen source layer 184 and the gate dielectric layer 182. In some cases, the halogen source layer 184 is not in direct contact with the gate dielectric layer 182. In some embodiments, the halogen source layer 184 has a thickness in a range from about 1 Å to about 10 Å. In some other embodiments, the halogen source layer 184 has a thickness in a range from about 2 Å to about 15 Å. In some cases, the halogen source layer 184 should not be too thick to ensure that a distance between the gate dielectric layer 182 and a subsequently formed work function layer is maintained in an acceptable range. In some embodiments, the thickness of the halogen source layer 184 is controlled to be smaller than about 15 Å. In some other embodiments, the thickness of the halogen source layer 184 is controlled to be smaller than about 10 Å.

The halogen source layer 184 may be used to prove halogen elements (or ions) to an interface between the fin structure 120 and the interfacial layer 181. The halogen elements (or ions) may be able to repair defects (such as dangling bonds) at the interface between the fin structure 120 and the interfacial layer 181. For example, the halogen elements or ions from the halogen source layer 184 may diffuse through the gate dielectric layer 182 and the interfacial layer 181 to reach the interface and repair the defects. As a result, the performance and reliability of the semiconductor device structure are improved. For example, the carrier mobility of the fin structure 120 is improved and becomes more stable.

In some embodiments, the halogen source layer 184 includes one or more kinds of halogen elements (or ions). In some embodiments, the halogen source layer 184 includes fluorine (F), chlorine (Cl), bromine (Br), another suitable element (or ion), or a combination thereof. In some embodiments, the halogen source layer 184 includes oxygen (O). In these cases, the halogen source layer 184 may also serve as an oxygen source layer. The oxygen elements (or ions) from the halogen source layer 184 may enter the gate dielectric layer 182 to repair defects (such as oxygen vacancies) in the gate dielectric layer 182. The quality of the gate dielectric layer 182 is therefore improved.

In some embodiments, the halogen source layer 184 includes a metal element. In some embodiments, the halogen source layer 184 includes titanium (Ti), tantalum (Ta), another suitable element, or a combination thereof. In some embodiments, the halogen layer 184 is electrically conductive. In some embodiments, the conductivity of the halogen layer 184 is greater than that of the gate dielectric layer 182 or the interfacial layer 181. In some embodiments, the halogen source layer 184 is a Ti—N—O— and -F-containing layer, a Ta—N—O-and-F-containing layer, a Ti—N-and-F-containing layer, a Ta—N-and-F-containing layer, another suitable layer, or a combination thereof.

In some embodiments, the halogen source layer 184 is formed over the gate dielectric layer 182 using an ALD process, a CVD process, another applicable process, or a combination thereof. In some embodiments, the formation of the halogen source layer 184 involves a thermal process, an in-situ ash process, an ex-situ ash process, a plasma process, another applicable process, or a combination thereof. In some embodiments, the halogen source layer 184 is a metal-containing layer doped with a halogen element. In some embodiments, the halogen source layer 184 is a metal nitride layer doped with a halogen element. In some embodiments, the halogen source layer 184 is a halogen-doped region within a material layer. For example, the halogen source layer 184 is a halogen-doped region within a material nitride layer. In these cases, the formation of the halogen source layer 184 involves an ALD process, a CVD process, an implantation process, a diffusion process, another applicable process, or a combination thereof.

In some embodiments, the halogen source layer 184 has an atomic concentration of a halogen element, such as fluorine. In some embodiments, the atomic concentration of the halogen element in the halogen source layer 184 is substantially uniform. In some other embodiments, the atomic concentration of the halogen element in the halogen source layer 184 is not uniform. In some embodiments, the atomic concentration of the halogen element in the halogen source layer 184 gradually becomes smaller along a direction from a top of the halogen source layer 184 towards the gate dielectric layer 182.

As shown in FIG. 2C, a capping layer 186 is deposited over the halogen source layer 184, in accordance with some embodiments. The capping layer 186 may be used to protect the structures below the capping layer 186. The capping layer 186 may prevent oxygen above the capping layer 186 from entering the gate dielectric layer 182 and the interfacial layer 181 during subsequent processes that may involve a thermal operation. Therefore, the thickness of the gate dielectric layer 182 or the interfacial layer 181 may remain substantially the same.

In some embodiments, the capping layer 186 includes a metal element and an oxygen element. In some embodiments, the capping layer 186 is made of titanium nitride, tantalum nitride, another suitable material, or a combination thereof. In some embodiments, the capping layer 186 is thicker than the halogen source layer 184. In some embodiments, the capping layer 186 has a thickness in a range from about 10 Å to about 30 Å. In some embodiments, the capping layer 186 is deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof. In some other embodiments, the capping layer 186 is not formed.

In some embodiments, the capping layer 186 is formed after the formation of the halogen source layer 182. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the capping layer 186 is formed before the formation of the halogen source layer 182.

FIGS. 5A-5B are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 5A, the capping layer 186 is deposited over the gate dielectric layer 182 before the formation of the halogen source layer 184, in accordance with some embodiments. Afterwards, a doping process 502 is performed on the capping layer 186, as shown in FIG. 5A in accordance with some embodiments. In some embodiments, the doping process 502 is an implantation process.

As shown in FIG. 5B, the doping process 502 dope a portion of the capping layer to forms the halogen source layer 184 within the capping layer 186, in accordance with some embodiments. In these cases, the halogen source layer 184 is also a halogen-doped region within the capping layer 186. The position (or depth) of the halogen source layer 184 within the capping layer 186 may be controlled through tuning the process parameter of the doping process 502. For example, the implantation energy and/or dosage may be varied to control the position of the halogen source layer 184. In some embodiments, the doping process 502 is fine-tuned such that the halogen source layer 184 (the halogen-doped region) is in direct contact with the gate dielectric layer 182. In some embodiments, the atomic concentration of the halogen element in the halogen source layer 184 (the halogen-doped region) gradually becomes smaller along a direction from a top of the halogen source layer 184 towards the gate dielectric layer 182. In some embodiments, since the halogen source layer 184 is a doped region within the capping layer 186, the distance between the fin structure 120 and a subsequently formed work function layer does not increase after the formation of the halogen source layer 184. The performance of the semiconductor device structure is therefore ensured.

Many variations and/or modifications can be made to embodiments of the disclosure. FIG. 6 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, the halogen source layer 184 is not in direct contact with the gate dielectric layer 182, as shown in FIG. 6 . In some embodiments, the halogen source layer 184 is a halogen-doped region that is formed within the capping layer 186. As shown in FIG. 6 , the halogen source layer 184 (the halogen-doped region) is between an upper portion 186 b and a lower portion 186 a of the capping layer 186, in accordance with some embodiments.

As shown in FIG. 2C, a barrier layer 187 is deposited over the capping layer 186, in accordance with some embodiments. The barrier layer 187 may be made of tantalum nitride, titanium nitride, another suitable material, or a combination thereof. In some embodiments, the barrier layer 187 has a thickness in a range from about 8 Å to about 12 Å. In some embodiments, the barrier layer 187 is deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof. In some other embodiments, the barrier layer 187 is not formed.

Afterwards, a work function layer 188 is deposited over the barrier layer 187, as shown in FIG. 2C in accordance with some embodiments. In some embodiments, the work function layer 188 conformally covers the fin structure 120. The work function layer 188 is used to provide the desired work function for transistors to enhance device performance, such as improved threshold voltage. In some embodiments, the work function layer 188 is an n-type metal layer capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV. In some embodiments, the work function layer 188 is a p-type metal layer capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV.

The n-type metal layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type metal layer includes titanium nitride, tantalum, tantalum nitride, other suitable materials, or a combination thereof. The p-type metal layer may include metal, metal carbide, metal nitride, other suitable materials, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof.

The work function layer 188 may also be made of hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combination thereof. The thickness and/or the compositions of the work function layer 188 may be fine-tuned to adjust the work function level. For example, a titanium nitride layer may be used as a p-type metal layer or an n-type metal layer, depending on the thickness and/or the compositions of the titanium nitride layer. In some embodiments, the work function layer 188 is a stack of multiple sub-layers. In some embodiments, the work function layer 188 is deposited using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof.

Afterwards, a glue layer (or a wetting layer) 189 is deposited over the work function layer 188, as shown in FIG. 2C in accordance with some embodiments. The glue layer (or a wetting layer) 189 may be used to facilitate a subsequent formation of a conductive filling layer. The glue layer (or the wetting layer) 189 may be made of cobalt, titanium nitride, tantalum nitride, another suitable material, or a combination thereof. In some embodiments, the glue layer (or the wetting layer) 189 is deposited using a CVD process, an electroplating process, a PVD process, an electroless plating process, another applicable process, or a combination thereof. In some other embodiments, the glue layer (or the wetting layer) 189 is not formed.

Afterwards, a conductive filling layer 190 is deposited over the glue layer (or the wetting layer) 189 to fill the recess 210, as shown in FIG. 2C in accordance with some embodiments. In some embodiments, the conductive filling layer 190 is made of tungsten, aluminum, copper, gold, platinum, another suitable material, or a combination thereof. In some embodiments, the conductive filling layer 190 is deposited using a CVD process, an electroplating process, a PVD process, an electroless plating process, another applicable process, or a combination thereof.

As shown in FIG. 2D, a planarization process is performed to remove the portions of the metal gate stack layers outside of the recess 210, in accordance with some embodiments. As a result, the remaining portions of the metal gate stack layers together form a gate stack 195 (a metal gate stack), as shown in FIGS. 1D and 2D in accordance with some embodiments. In some embodiments, the gate stack 195 covers a portion of the fin structure 120. In some embodiments, the halogen source layer 184 conformally covers the sidewalls and the top of the fin structure 120. Therefore, the halogen element from the halogen source layer 184 (or halogen-doped region) may diffuse to the surface of the fin structure 120 to repair defects at the sidewalls and the top of the fin structure 120. The performance and reliability of the semiconductor device structure are significantly improved. In some embodiments, some halogen elements from the halogen source layer 184 exist in the gate dielectric layer 182, the interfacial layer 181, and or a surface portion of the fin structure 120.

Many variations and/or modifications can be made to embodiments of the disclosure. FIG. 3 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, FIG. 3 shows a portion of the gate stack 195. In some embodiments, the halogen source layer 184 is between the gate dielectric layer 182 and the work function layer 188. However, the halogen source layer 184 is not limited to be between the gate dielectric layer 182 and the capping layer 186. In some embodiments, the capping layer 186 is between the gate dielectric layer 182 and the halogen source layer 184. In some embodiments, the halogen source layer 184 is a deposited layer formed after the formation of the capping layer 186. In some embodiments, the halogen source layer 184 is a doped region within an upper portion of the capping layer 186.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, two or more halogen source layers are formed between the gate dielectric layer 182 and the work function layer 188.

FIG. 4 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, two or more halogen source layers are formed between the gate dielectric layer 182 and the conductive filling layer 190. In some embodiments, halogen source layers 184 a and 184 b are formed on the bottom and the top of the capping layer 186, respectively. In some embodiments, the halogen source layers 184 a and 184 b are deposited layers. In some embodiments, the halogen source layers 184 a and 184 b are halogen doped regions below and above the capping layer 186. In some embodiments, the halogen source layers 184 a and 184 b contain different kinds of halogen elements. In some other embodiments, the halogen source layers 184 a and 184 b contains the same kind of halogen element.

Many variations and/or modifications can be made to embodiments of the disclosure. FIG. 7 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments, a metal gate stack 195′ is formed over the semiconductor substrate 100. Unlike the gate stack 195, the metal gate stack 195′ is not formed by replacing a dummy gate stack. In some embodiments, the gate stack layers including the layers 181, 182, 184, 186, 187, and 188 are formed over the semiconductor substrate 100 and patterned to form the metal gate stack 195′. The halogen source layer 184 may provide halogen elements (or ions) to the surface of the semiconductor substrate 100 below the interfacial layer 181. The defect at the interface between the semiconductor substrate 100 and the interfacial layer 181 may therefore be repaired. For example, the number of dangling bonds at the interface is reduced. As a result, the performance and the reliability of the semiconductor device structure are improved.

Embodiments of the disclosure form a semiconductor device structure with a gate stack including a halogen source layer formed between a gate dielectric layer and a top of the gate stack. The halogen source layer is a deposited layer or a doped region over the gate dielectric layer. The halogen source layer is configured to provide a halogen element or ion to a surface of a semiconductor fin or a semiconductor substrate below the gate dielectric layer. The halogen element may repair defects (such as dangling bonds) at the surface of the semiconductor fin or the semiconductor substrate. Therefore, the performance and the reliability are greatly improved.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer, a capping layer, and a work function layer, and the capping layer is between the gate dielectric layer and the work function layer. The semiconductor device structure also includes a halogen-doped region within the capping layer.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate and forming a cap layer over the gate dielectric layer. The method also includes forming a halogen source layer over the gate dielectric layer. The method further includes forming a work function layer over the cap layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

1-20. (canceled)
 21. A method of fabricating a semiconductor device structure, comprising: providing a semiconductor structure having a fin extending from the semiconductor structure; forming a dummy gate structure over the fin; recessing the fin adjacent the dummy gate structure to form a recessed fin portion; epitaxially growing a source/drain region on the recessed fin portion; removing the dummy gate structure to form an opening; forming a gate dielectric layer in the opening, wherein the gate dielectric is formed on a plurality of channel surfaces formed from the fin; and forming each of a capping layer, a halogen source layer, a barrier layer, and a work function layer over the gate dielectric, wherein the halogen source layer interposes the capping layer and the gate dielectric layer, wherein the gate dielectric layer is between the semiconductor substrate and the halogen source layer, and wherein the work function layer is over the capping layer.
 22. The method of claim 21, wherein the forming the halogen source layer includes forming a material having an atomic concentration of a halogen element.
 23. The method of claim 22, wherein the atomic concentration of the halogen element in the halogen source layer gradually becomes smaller along a direction from a surface of the halogen source layer towards the gate dielectric layer.
 24. The method of claim 21, wherein the capping layer is formed directly on the gate dielectric layer.
 25. The method of claim 21, further comprising: depositing a conductive filling layer over the gate dielectric layer; and performing a chemical mechanical polish (CMP) on the conductive filling layer.
 26. The method of claim 21, wherein the forming the dummy gate structure over the fin includes depositing spacers on sidewalls of the dummy gate structure.
 27. The method of claim 26, wherein the spacers are deposited on a dummy gate dielectric layer of the dummy gate structure.
 28. The method of claim 27, wherein removing the dummy gate structure to form the opening includes removing a center portion of the dummy gate dielectric layer to expose a semiconductor surface in the opening while spacers are disposed on edge regions of the dummy gate dielectric layer.
 29. A semiconductor device structure, comprising: a semiconductor surface; a gate stack over a center portion of the semiconductor surface, wherein the gate stack comprises: a gate dielectric layer; a cap layer over the gate dielectric layer, wherein the cap layer has an upper portion and a lower portion; a halogen source layer between the upper portion of the cap layer and the lower portion of the cap layer; and a work function layer over the upper portion of the cap layer; and a dielectric layer over a first region of the semiconductor surface and a second region of the semiconductor surface, wherein the center portion interposes the first and second regions.
 30. The semiconductor device structure of claim 29, wherein the dielectric layer includes one of silicon oxide or silicon nitride.
 31. The semiconductor device structure of claim 29, wherein at least one of the gate dielectric layer, the cap layer and the halogen source layer have a U-shaped configuration.
 32. The semiconductor device structure of claim 29, wherein the halogen source layer includes at least one of chlorine or bromine.
 33. The semiconductor device structure of claim 32, wherein the halogen source layer further includes oxygen and at least one of titanium or tantalum.
 34. The semiconductor device structure of claim 29, wherein a spacer element is disposed on the dielectric layer over the first region and the second region.
 35. The semiconductor device structure of claim 34, wherein the spacer element interfaces a sidewall of the gate stack.
 36. A method of fabricating a semiconductor device structure, comprising: providing a semiconductor surface above a substrate; forming a dummy gate structure including a dielectric layer over the semiconductor surface; forming spacers adjacent the dummy gate structure, wherein the spacers are formed over the dielectric layer; removing the dummy gate structure to form an opening exposing a region of the semiconductor surface, wherein the opening extends between spacers; depositing a gate dielectric in the opening over the region of the semiconductor surface; and forming a capping layer, a halogen source layer, and a work function layer over the gate dielectric, wherein the halogen source layer interposes the capping layer and the gate dielectric layer, wherein the gate dielectric layer is between the semiconductor surface and the halogen source layer, and wherein the work function layer is over the capping layer.
 37. The method of claim 36, wherein the halogen source layer is formed in direct contact with the gate dielectric layer.
 38. The method of claim 36, wherein depositing the gate dielectric in the opening includes forming the gate dielectric having a U-shape.
 39. The method of claim 36, wherein the formed opening includes a bottom surface of the semiconductor surface and sidewalls of the spacers, and wherein the forming the gate dielectric in the opening includes forming the gate dielectric along the bottom surface and the sidewalls of the opening.
 40. The method of claim 39, further comprising: performing a planarization process after forming the gate dielectric in the opening, wherein the planarization process removes a portion of the gate dielectric. 